1. Field of the Invention
The present invention relates to current mode circuitry employed for creation of poles and zeros that are combined with feedback to create complex filter functions. More particularly, the present invention relates to a cell structure having a current mirror and a capacitor to create a single real pole with which virtually any filter function can be realized using scale factors, summers, feedback and feedforward circuits. The term “real” as used herein references the “real” axis in the complex plane.
2. Background Information
Current mode signal processing is common due to its advantages in low voltage applications and where high speed and/or small size are important compared to voltage mode circuitry. Diode connected devices exhibit such characteristics in current mirror configurations. Diode connected circuits also exhibit few internal nodes with parasitic poles thus increasing operating frequencies.
Diode connected devices compared to voltage mode circuits, however, generally have higher noise and distortion for a given device size and bias current (power dissipation).
FIG. 1 illustrates known MOS current mirror operation. The PMOS devices M5 to M8 provide bias current while NMOS devices M1 to M4 comprise the current mirror. As known to those skilled in the art, the cascade configuration illustrated by FIG. 1 generally reduces the gain error implicit when the output of a first current source drives the input of a second. If g1 is the output conductance of the first and g2 the input conductance of the second, a gain error of g1/(g1+g2) is introduced. Using the cascode g1 is made small reducing this error.
The drain current of M1 is IB1+id1, where IB1 is the output from the PMOS current source, M5 and M7. The time varying component of the drain current through M1, also referred to as the small signal, is id1, which equals i(in). Also, the small signal current through M2 is id2 which equals −i(out) (as illustrated). The current id2 is a current mirror of id1, and the gain A of a current mirror is normally the width ratio of the MOS devices in the output leg compared to that in the input leg, with corresponding lengths being equal. So considering the mirrors forming Ib1 and Ib2, A is equal to the width of M8 and M6 compared to the widths of M7 and M5, with equal lengths. In practical applications, the gain A is used to provide gain, attenuations and scale factors for current used in feedback or feed forward applications. Thus id2=(A)id1, and i(out)=−(A)i(in), and with A=1, i(out)=−i(in). In the following discussions, A=1, but other values may be used to advantage.
It is well known that the basic current mirror is very linear of a wide signal dynamic range relative to its bias current. If M1 and M2, of FIG. 1, have equal gate to source and drain to source voltages, Vgs and Vds, respectively, and the substrates are biased to eliminate body effects, the mirrors will demonstrate a very linear current transfer ratio. This also is a benefit of the cascade structure. In practical applications, it is possible to have up to 80 db (four decades, or 10,000/1) THD (Total Harmonic Distortion) where the small signal current may run up to 70% of the bias current. Careful design will require that the drain to source voltage of the mirrors is significantly above the Veff of the MOS device, where Veff=Vgs−VT. VT is the threshold voltage of the device.
Using the basic current mirror of FIG. 1, FIG. 2A illustrates adding a capacitor, C, to realize a single real pole circuit. FIG. 2B is a small signal equivalent circuit representation of the circuit of FIG. 2A. FIG. 2A is a single ended circuit where the capacitor C provides a single pole structure. M1 is a diode connected MOS with the cascode M3 structure that may be used to set a DC level. M2 is a current mirror of M1 and provides an output current i(o) via the drain of the cascode M4.
The prior art circuits of FIGS. 2A and B are more fully described in a paper by Sterling L. Smith and Edgar Sanchez-Sinencio, entitle “Low voltage integrators for High-Frequency CMOS Filters Using Current Mode Techniques”, published in IEEE Transactions on Circuits and Systems—II: Analog and Digital signal Processing, Vol. 43, No. 1, January 1996. This paper is hereby incorporated herein by reference. Please note that this paper and the present invention describe practical embodiments using differential inputs and outputs, but the present invention will find advantageous application as a single circuit. Obviously, differential applications double the physical size of the circuitry and the power dissipated, so single ended use is preferred in some applications. The following descriptions of single ended circuits are directly applicable to differential circuits by simple replicating the single ended circuits.
Poles and zeros are well known in the electronic arts and a basic working understanding of how they operate follows. Typically poles and zero are defined with respect to transfer functions (out/in) in the complex s or LaPlacian plane. Transient responses are included in the s plane whereas in the jω plane, that is often used, only the gain/phase characteristics of a transfer function are illustrated. A series low pass RC (resistor in series with a capacitor), with the voltage signal taken across the capacitor, and an input voltage signal coupled to the distal side of the resistor from the capacitor will demonstrate a one pole voltage gain/frequency transfer function.
Many papers and text exist describing such poles and zeros and those skilled in the art will understand their use as described in the present invention.
As mentioned above, the more practical circuit of FIG. 1B is described below in more detail. A time varying current signal i(in) is input to the capacitor C and a time varying signal i(o) is output from the drain of M4. This circuit represents the one pole fundamental cell mentioned above. This circuit is incorporated into feedback/feedforward designs to create complex poles and zeros pairs useful in complex filter functions.
By inspection of FIG. 2B,i(in)=id1+ic; and  Eq. 1i(out)=−id2=−id1.  Eq. 2
The small signal voltage across the capacitor of FIG. 2B is (id1/gm), and so the current ic through the capacitor is (id1/gm)Cs. So, from Eq. 1,
i(in)=id1+(id1/gm)Cs=id1(1+Cs/gm). Or,
id1=i(in)/(1+Cs/gm). Substituting this into Eq. 2, we have:
id1=−i(out)=i(in)/(1+Cs/gm), or the transfer function of the output divided by the input yields:i(out)/i(in)=−1/(1+Cs/gm)=−(gm/C)/(s+gm/C).   Eq. 3
By inspection there is a single real pole in Eq. 3 at s=−gm/C. The dimensions for s are radian/sec.
Distortion
Since the input signal current divides between the capacitor and the diode connected MOS device, and the capacitor voltage is the gate to source voltage Vgs of M1 in FIG. 2A, which introduces the major distortion factor. Generally, for a MOS device the Vgs can be represented by the threshold voltage VT plus the square root of the drain current divided by a constant, B. The constant B equal u(Cox)W/2L, where Cox is a capacitor factor of the oxide that forms the dielectric, u is a mobility factor and W is the effective channel width and L the length. Considering on the small signal of time varying portion of the Vc=Vgs=Veff=(id/B)½.
Thus, i(in)=ic+id1, where, i(c)=C(dVeff/dt)=C(d(id1/B)½/dt). Carrying out the operations, we have:i(in)=id1(id1)½+C/2(B)½  Eq. 4
The conversion from i(in) to i(out) involves, first a conversion of i(in) to id1, and then from id1 to id2 and from id2 to i(out). With A=1, and other conditions described above, in on embodiment, i(out)=−id1. From Eq. 4 the relationship of i(in) to id1 is non-linear, so the relationship from i(in) to i(out) is non-linear.
It is an objective of the present invention to reduce this non-linearity.
The present invention improves linearity of the current prior art circuits. By improving linearity, the present invention advantageously improves noise for a given distortion level. Moreover, the present invention improves high frequency performance by using smaller devices and therefore lower parasitic capacitors, lower bias currents (and thus lower power dissipation) and use of less chip area and thus lower cost.